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| Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller with 128 KByte Flash EPROM C167CR-16F Data Sheet 03.97 Advance Information Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller with 128 KByte Flash EPROM C167CR-16F Data Sheet 03.97 Advance Information C167CR-16F Revision History: Previous Releases: Page Subjects Original Version 03.97 (Advance Information) - Controller Area Network (CAN): License of Robert Bosch GmbH Edition 03.97 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation Balanstrae 73, D-81541 Munchen. (c) Siemens AG 1997. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Offices of Siemens Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the type in question please contact your nearest Siemens Office, Components Group. Siemens AG is an approved CECC manufacturer. C166-Family of High-Performance CMOS 16-Bit Microcontrollers Advance Information C167CR-16F 16-Bit Microcontroller C167CR-16F High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via on-chip PLL or via direct clock input Up to 16 MByte Linear Address Space for Code and Data 2 KByte On-Chip Internal RAM (IRAM) 2 KByte On-Chip Extension RAM (XRAM) 128 KByte On-Chip Flash EPROM with Bank Erase Feature and Read Protection Dedicated Flash Control Register with Operation Lock Mechanism 12 V External Flash Programming Voltage Flash Program Verify and Erase Verify Modes with 1000 Program/Erase Cycles Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed Address/Data Buses with 5 Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns 16-Channel 10-bit A/D Converter with 9.7s Conversion Time Two 16-Channel Capture/Compare Units and one 4-Channel PWM Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) On-Chip CAN Interface with 15 Message Objects (Full-CAN/Basic-CAN) Programmable Watchdog Timer Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards q On-Chip Bootstrap Loader q 144-Pin MQFP Package (EIAJ) q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q This document describes the SAB-C167CR-16FM and the SAF-C167CR-16FM . For simplicity all versions are referred to by the term C167CR-16F throughout this document. 1 03.97 C167CR-16F 06May97@14:10h Intermediate Version Introduction The C167CR-16F is a new derivative of the Siemens C16x Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM, on-chip Flash memory and clock generation via PLL. VPP C167CR16F Figure 1 Logic Symbol Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, ie. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C167CR-16F please refer to the Product Information Microcontrollers", which summarizes all available microcontroller variants. q q q q Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 2 06May97@14:10h Intermediate Version C167CR-16F Pin Configuration (top view) C167CR-16F A22/CAN_TxD /CAN_RxD Figure 2 3 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Pin Definitions and Functions Symbol P6.0 - P6.7 Pin Input (I) Number Output (O) 18 I/O Function Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The following Port 6 pins also serve for alternate functions: Chip Select 0 Output P6.0 CS0 ... ... ... Chip Select 4 Output P6.4 CS4 External Master Hold Request Input P6.5 HOLD Hold Acknowledge Output P6.6 HLDA Bus Request Output P6.7 BREQ Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output ... ... ... P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out ... ... ... P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out 1 ... 5 6 7 8 P8.0 - P8.7 916 O ... O I O O I/O 9 ... 16 P7.0 - P7.7 19 26 I/O ... I/O I/O 19 ... 22 23 ... 26 O ... O I/O ... I/O Semiconductor Group 4 06May97@14:10h Intermediate Version C167CR-16F Pin Definitions and Functions (cont'd) Symbol P5.0 - P5.15 Pin Input (I) Number Output (O) 27 - 36 39 - 44 I I Function Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out, EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input 39 40 41 42 43 44 P2.0 - P2.15 47 - 54 57 - 64 I I I I I I I/O 47 ... 54 57 ... 64 I/O ... I/O I/O I ... I/O I I 5 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Pin Definitions and Functions (cont'd) Symbol P3.0 - P3.13, P3.15 Pin Input (I) Number Output (O) 65 - 70, 73 - 80, 81 I/O I/O I/O Function Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE Ext. Memory High Byte Write Strobe WRH P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.4 A20 Segment Address Line P4.5 A21 Segment Address Line, CAN_RxD CAN Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7 A23 Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access. 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 P4.0 - P4.7 85 - 92 I O I O I I I I I/O I/O O I/O O O I/O O I/O 85 ... 89 90 91 92 RD 95 O ... O O I O O O O Semiconductor Group 6 06May97@14:10h Intermediate Version C167CR-16F Pin Definitions and Functions (cont'd) Symbol WR/ WRL Pin Input (I) Number Output (O) 96 O Function External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C167CR-16F to begin instruction execution out of external memory. A high level forces execution out of the internal Flash memory. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 READY 97 I ALE 98 O EA 99 I PORT0: P0L.0 - P0L.7, P0H.0 P0H.7 I/O 100 - 107 108, 111-117 7 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Pin Definitions and Functions (cont'd) Symbol PORT1: P1L.0 - P1L.7, P1H.0 P1H.7 Pin Input (I) Number Output (O) I/O 118 - 125 128 - 135 Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C167CR-16F. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167CR-16F to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the Analog/Digital converter. Reference ground for the Analog/Digital converter. XTAL1: 132 133 134 135 XTAL1 XTAL2 138 137 I I I I I O RSTIN 140 I RSTOUT 141 O NMI 142 I VAREF VAGND 37 38 - Semiconductor Group 8 06May97@14:10h Intermediate Version C167CR-16F Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Number Output (O) 84 Function Flash programming voltage. This pin accepts the programming/erase voltage for the C167CR-16F (VPP = 12 V). During normal operation (programming voltage VPP = 12 V not required) this pin must be connected to VCC. Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode. VPP VCC 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 VSS Digital Ground. Note: All VSS pins and all VCC pins must be connected to the system ground and the power supply, respectively. 9 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Functional Description This document only describes specific properties of the C167CR-16F, eg. Flash memory functionality or specific DC and AC Characteristics, while for all other descriptions common for the C167CR-16F and the C167CR, eg. functional description, it refers to the respective Data Sheet for the Non-Flash device. A detailled description of the C167CR-16F's instruction set can be found in the "C16x Family Instruction Set Manual". Memory Organization The memory space of the C167CR-16F is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. 2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C16x family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed. 128 KBytes of on-chip Flash memory are provided to store user code or (read only) data. The Flash memory is divided into 4 blocks of different size which can be programmed/erased separately. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. Semiconductor Group 10 06May97@14:10h Intermediate Version C167CR-16F Flash Memory Overview The C167CR-16F provides 128 KBytes of electrically erasable and reprogrammable non-volatile Flash EPROM on-chip for code or constant data. A separate Flash Control Register (FCR) has been implemented to control Flash operations like programming or erasure. For programming or erasing an external 12 V programming voltage must be applied to the VPP pin. Flash programming and erasure is only possible during writing mode which is entered via a special key code sequence (Unlock sequence) to avoid unintended Flash operations. The Flash memory is organized in blocks 32 bits wide which allows even double-word instructions to be fetched in just one machine cycle. The entire Flash memory is divided into four blocks with different sizes (48/48/24/8 KByte). This allows to erase each block separately, when only parts of the Flash memory need to be reprogrammed. Word or double word programming typically takes 100 s, block erasing typically takes 1 s (@ 20 MHz CPU clock). The Flash memory features a typical endurance of 1000 erasing/programming cycles. Erased Flash memory cells contain all `1's, as known from standard EPROMs. The Flash memory can be programmed both in an appropriate programming board and in the target system which provides a lot of flexibility. The C167CR-16F's on-chip bootstrap loader may be used to load and start the programming code. Any code that programs or erases Flash memory locations must be executed from memory outside the on-chip Flash memory itself (on-chip RAM or external memory). To save the customer's know-how, a Flash memory protection option is provided in the C167CR16F. If this was activated once, Flash memory contents cannot be read from any location outside the Flash memory itself (see section Flash Protection"). The lower 32 KBytes of the on-chip Flash memory of the C167CR-16F can be mapped to either segment 0 (00'0000H to 00'7FFFH) or segment 1 (01'0000H to 01'7FFFH) during the initialization phase to allow external memory to be used for additional system flexibility. The upper 96 KBytes of the on-chip Flash memory are assigned to locations 01'8000 H to 02'FFFFH. In standard mode (the normal operating mode) the Flash memory appears like the standard on-chip ROM of C167 devices with the same timing and functionality. Instruction fetches and data operand reads are performed with all addressing modes of the C16x instruction set. In writing mode specific blocks of the on-chip Flash memory can be programmed (doublewords or words) or erased (banks). Writing mode is entered via a special key lock sequence and provides full access to the Flash Control Register (FCR). For programming as well as for erasing there are specific verify modes that allow to validate the previous operation in order to ensure secure Flash handling. The following terminology is used in this document: Flash WRITING means changing the state of the floating gate. Flash PROGRAMMING means loading electrons onto the floating gate. Flash ERASING means removing electrons from the floating gate. Please refer to section Fundamentals of Flash Technology". 11 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version 02'FFFFH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA : Bank 3 Bank 2 02'E000H 02'8000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA 2 02'0000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A Bank 1 01'C000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA01'8000 A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 0x'0000H 01'0000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A 00'0000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A 1 Bank 0 0 Memory Segments Flash Banks Figure 3 Flash Memory Overview Semiconductor Group 12 06May97@14:10h Intermediate Version C167CR-16F Flash Memory Configuration Upon reset the default memory configuration of the C167CR-16F is determined by the state of its EA pin. When EA is high the startup code is fetched from the on-chip Flash memory, when EA is low the internal ROM is disabled and the startup code is fetched from external memory. In order to access the on-chip Flash memory after booting from external memory the internal ROM must be enabled via software by setting bit ROMEN in register SYSCON. The lower 32 KBytes of the Flash memory can be mapped to segment 0 or to segment 1, controlled by bit ROMS1 in register SYSCON. Mapping to segment 1 preserves the external memory containing the startup code, while mapping to segment 0 replaces the lower 32 KBytes of the external memory with on-chip Flash memory. In this case a valid vector table must be provided. As the on-chip Flash memory covers more than segment 0 segmentation should be enabled (by clearing bit SGTDIS in register SYSCON) in order to ensure correct stack handling when branching to the upper segments. Whenever the internal memory configuration of the C167CR-16F is changed (enable, disable, mapping) the following procedure must be used to ensure correct operation: q q q Configure the internal ROM as required Execute an inter-segment branch (JMPS, CALLS, RETS) Reload all four DPP registers Note: Instructions that configure the internal ROM may only be executed from internal RAM or from external memory, not from the ROM itself. Register SYSCON can only be modified before the execution of the EINIT instruction. The C167CR-16F's Bootstrap Loader provides a mechanism to load the startup code and/or the Flash progamming routines from a remote code source via the serial interface without requiring additional external memory. This allows for firmware updates of the Flash memory for program and/ or data values. The Flash Control Register (FCR) In standard operation mode the Flash memory can be accessed like the normal maskprogrammable on-chip ROM of the C167CR. So all appropriate direct and indirect addressing modes can be used for reading the Flash memory. All programming or erase operations of the Flash memory are controlled via the 16-bit Flash Control Register FCR. To prevent unintentional writing to the Flash memory the FCR is locked and inactive during standard operation mode. Before a valid access to the FCR is enabled, the Flash memory writing mode must be entered. This is done via a special key code instruction sequence. Note: The FCR is no real register (SFR or GPR) but is rather virtually mapped into the active address space of the Flash memory. All even direct (mem) word accesses refer to the FCR (no byte- or bit-addressing), while all indirect ([Rwn]) accesses refer to the Flash memory array itself. ROM mapping and DPP referencing must be considered for FCR accesses. 13 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version FCR (Even Flash Address) 15 FWM SET rw 14 rw 13 rw 12 rw 11 rw 10 rw 9 BE rw 8 7 WDW W rw 6 5 4 VPP REV r Reset Value: 00X0H*) 3 2 1 0 FC FBUSY VPP RPROT FEE FWE rw r/w rw rw CKCTL rw Bit FWE Function Flash Write Enable Bit (see description below) 0 : Flash write operations (program / erase) disabled 1 : Flash write operations (program / erase) enabled Flash Erase Enable Bit (Significant only, when FWE='1', see description below) 0 : Flash programming mode selected 1 : Flash erase mode selected Flash Busy Bit (On read accesses) 0 : No Flash write operation in progress 1 : Flash write operation in progress Flash Read Protection Activation Bit (On write accesses) 0 : Deactivates Flash read protection 1 : Activates Flash read protection, if this is enabled Flash Control VPP Bit 0 : No VPP failure occurred during a Flash write operation 1 : VPP failure occurred during a Flash write operation Flash VPP Revelation Bit 0 : No valid VPP applied to pin VPP 1 : VPP applied to pin VPP is valid Internal Flash Timer Clock Control Determines the width of an internal Flash write or erase pulse Word / Double Word Writing Bit (significant only in programming mode) 0 : 16-bit programming operation 1 : 32-bit programming operation Bank Erase Select (significant only in erasing mode) Selects the Flash Bank to be erased Flash Writing Mode Set Bit (see description below) 0 : Exit Flash writing mode, return to standard mode 1 : Stay in Flash writing mode FEE FBUSY RPROT FCVPP VPPREV CKCTL WDWW BE FWMSET *) The reset value of bit VPPREV depends on the voltage on pin VPP. The selection of Flash Operation and Read Mode is done via the three bits FWE, FEE and FWMSET. The table below shows the combinations for these bits to select a specific function: Semiconductor Group 14 06May97@14:10h Intermediate Version C167CR-16F FWMSET 1 1 1 0 FEE 1 0 X X FWE 1 1 0 X Flash Operation Mode Erasing mode Programming mode Non-Verify mode Standard mode Flash Read Mode Erase-Verify-Read via [Rn] Program-Verify-Read via [Rn] Normal Read via [Rn] Normal Read via [Rn] or mem FWE enables/disables write operations, FEE selects erasing or programming, FWMSET indicates writing mode and is set automatically once the writing mode is entered. Bits FWE and FEE select an operation, but do not directly execute this operation. Note: Watch the FWMSET bit when writing to register FCR (word access only) in order not to exit Flash writing mode unintentionally by clearing bit FWMSET. FBUSY: This read-only flag is set to `1' while a Flash programming or erasing operation is in progress. FBUSY is set via hardware when the respective program/erase command is issued. RPROT: This write-only Flash Read Protection bit determines whether Flash protection is active or inactive. RPROT is the only FCR bit which can be modified even in the Flash standard mode but only by an instruction executed from the on-chip Flash memory itself. Per reset, RPROT is set to `1'. Note: RPROT is only significant if the general Flash memory protection is enabled. FCVPP and VPPREV: These read-only bits allow to monitor the VPP voltage. The Flash Vpp Revelation bit VPPREV reflects the state of the VPP voltage in the Flash writing mode (VPPREV = `0' indicates that VPP is below the threshold value necessary for reliable programming or erasure, otherwise VPPREV = `1'). The Flash Control VPP bit FCVPP indicates if VPP fell below the valid threshold value during a Flash programming or erase operation (FCVPP = `1') and the operation therefore might not have been executed properly. FCVPP = `0' after such an operation indicates that no critical discontinuity on VPP has occurred. CKCTL: This Flash Timer Clock Control bitfield controls the width of the programming or erase pulses (TPRG) applied to Flash memory cells during the corresponding operation. The width of a single programming or erase pulse and the cumulated programming or erase time must not exceed certain values to avoid putting the Flash memory under critical stress (see table below). The pulse width and also the maximum number on programming or erase attempts allowed depends on the CPU clock frequency. Time Specification Maximum Programming Pulse Width Maximum Cumulated Programming Time Maximum Erase Pulse Width Maximum Cumulated Erase Time Limit Value 200 2.5 20 30 s ms ms s 15 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version In order not to exceed the limit values listed above, a specific CKCTL setting requires a minimum CPU clock frequency, as listed below. Setting of CKCTL 00 01 10 11 1) Length of TPRG 28 * 1/fCPU 211 * 1/fCPU 215 * 1/fCPU 218 * 1/fCPU TPRG @ fCPU = 20 MHz 12.8 s 102.4 s 1.64 ms 13.11 ms fCPUmin for programming 1.28 MHz 10.24 MHz ----- fCPUmin for erasing ( ( 12.8 KHz ) 1) 102.4 KHz ) 1) 1.64 MHz 13.11 MHz Please note that these are computed values. Actual values must respect the operational range specified for the C167CR-16F. The maximum number of allowed programming or erase attempts depends on the CPU clock frequency and on the CKCTL setting chosen in turn. This number results from the actual pulse width compared to the maximum pulse width (see above tables). The table below lists some sample frequencies, the respective recommended CKCTL setting and the resulting maximum number of program / erase pulses: fCPU CKCTL 1 MHz 10 MHz 16 MHz 20 MHz 00 00 00 00 Programming TPROG 128 s 12.8 s 8 s 6.4 s NPROGmax 19 195 312 390 CKCTL 01 10 10 10 Erasing TPROG 2.05 ms 3.28 ms 2.05 ms 1.64 ms NERASEmax 14648 9155 14648 18310 BE: The Flash Bank Erasing bit field determines the Flash memory bank to be erased (see table below). The physical addresses of the lower 32 KBytes of bank 0 depend on the Flash memory mapping chosen. BE setting 00 01 10 11 Bank 0 1 2 3 Size 48 KB 48 KB 24 KB 8 KB Addresses Selected for Erasure (x = 0 or 1) 0x'0000H to 0x'7FFFH / 01'8000H to 01'BFFFH 01'C000H to 01'FFFFH / 02'0000H to 02'7FFFH 02'8000H to 02'DFFFH 02'E000H to 02'FFFFH Semiconductor Group 16 06May97@14:10h Intermediate Version C167CR-16F Operation Modes of the Flash Memory There are two basic operation modes for Flash accesses: The standard and the writing mode. Submodes of the writing mode are the programming, the erase and the non-verify mode. Figure 4 Flash Operating Mode Transitions In Standard Mode the Flash memory can be accessed from any memory location (external memory, on-chip RAM or Flash memory) for instruction fetches and data operand reads. Data operand reads may use both direct 16-bit (mnemonic: mem) and indirect (mnemonic: [Rw]) addressing modes. Standard mode does not allow Flash write operations or accesses to the FCR except for the protection activation bit RPROT. Note: When Flash protection is active, data operands can be accessed only by instructions that are executed out of the internal Flash memory and branches to the Flash memory from locations outside are inhibited. The Flash Writing Modes must be entered for programming or erasing the Flash memory. The C167CR-16F enters these modes by a specific key code sequence, called UNLOCK sequence. In writing mode the used addressing mode decides whether the FCR or a Flash memory location is accessed. The FCR can be accessed with any direct access to an even address in the active address space of the Flash memory. Only word operand instructions are allowed for FCR accesses. Accesses to Flash memory locations must use indirect addressing to even addresses. direct 16-bit addressing mode: indirect addressing mode: mem --> [Rwn] --> 17 Access to FCR Access to Flash location Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version After entering writing mode the first erase or programming operation must not be started for at least 10 s. This absolute (!) delay time is required to set up the internal high voltage. In general, Flash write operations need a 12 V external VPP voltage to be applied to the VPP pin. It is not possible to erase or to program the Flash memory via code executed from the Flash memory itself. The respective code must reside within the on-chip RAM or within external memory. When programming or erasing `on-line' in the target system, some considerations have to be taken: While these operations are in progress, the Flash memory cannot be accessed as usual. Therefore care must be taken that no branch is taken into the Flash memory and that no data reads are attempted from the Flash memory during programming or erasure. If the Flash memory is mapped to segment 0, it must especially be ensured that no interrupt or hardware trap can occur, because this would implicitly mean such a `forbidden' branch to the Flash memory. Correct Flash operation is not guaranteed in this case. The UNLOCK sequence is a specific key code sequence, which is required to enable the writing modes of the C167CR-16F. The UNLOCK sequence must use identical values (see example below) and the two accesses must not be interrupted: MOV MOV CALL FCR, Rwn [Rwn], Rwn cc_UC, WAIT_10 ;Dummy write to the FCR ;Both operands use the same GPR ;Delay for 10 s (may be realized also by ;instructions other than a delay loop where Rwn can be any word GPR (R0...R15). [Rwn] and FCR must point to even addresses within the active address space of the Flash memory. Note: Data paging and Flash segment mapping, if active, must be considered in this context. In Flash Erase Mode (FEE='1', FWE='1') the C167CR-16F is prepared to erase the bank selected by the Bank Erase (BE) bit field in the FCR. The width of the erase pulses generated internally is defined by the Internal Flash Timer Clock Control (CKCTL) bit field of the FCR. The maximum number of erase pulses (ENmax) applied to the Flash memory is determined by software in the Flash erase algorithm. The chosen values for CKCTL and ENmax must guarantee a maximum cumulated erase time of 30 s per bank and a maximum erase pulse width of 10 ms. The Flash bank erase operation will not start before the erase command is given. This provides additional security for the erase operation. The erase command can be any write operation to a Flash location, where the data and the even address written to must be identical: MOV [Rwn], Rwn ; Both operands use the same GPR Upon the execution of this instruction, the Flash Busy (FBUSY) flag is automatically set to `1' indicating the start of the operation. End of erasure can be detected by polling the FBUSY flag. VPP must stay within the valid margins during the entire erase process. At the end of erasure the Erase-Verify-Mode (EVM) is entered automatically. This mode allows to check the effect of the erase operation (see description below). Note: Before the erase algorithm can be properly executed, the respective bank of the Flash memory must be programmed to all zeros (`0000H'). Semiconductor Group 18 06May97@14:10h Intermediate Version C167CR-16F In Flash Programming Mode (FEE='0', FWE='1') the C167CR-16F is prepared to program Flash locations in the way specified by the Word or Double Word Write (WDWW) bit in the FCR. The width of the programming pulses generated internally is defined by the Internal Flash Timer Clock Control (CKCTL) bit field of the FCR. The maximum number of programming pulses (PNmax) applied to the Flash memory is determined by software in the Flash programming algorithm. The chosen values for CKCTL and PNmax must guarantee a maximum cumulated programming time of 2.5 ms per cell and a maximum programming pulse width of 128 s. If 16-bit programming was selected, the operation will start automatically when a write instruction is executed, where the first operand specifies the address and the second operand the value to be programmed: MOV [Rwn], Rwm ;Program one word If 32-bit programming was selected, the operation will start automatically when the second of two subsequent write instructions is executed, which define the doubleword to be programmed. Note that the destination pointers of both instructions refer to the same even double word address. The two instructions must be executed without any interruption. MOV MOV [Rwn], Rwx [Rwn], Rwy ;Prepare programming of first word ;Start programming of both words Upon the execution of the second instruction (or the one and only in 16-bit programming mode), the Flash Busy (FBUSY) bit is automatically set to `1'. End of programming can be detected by polling the FBUSY bit. VPP must stay within the valid margins during the entire programming process. At the end of programming the Program-Verify-Mode (PVM) is entered automatically. This mode allows to check the effect of the erase operation (see description below). The Flash Verify-Modes Erase-Verify-Mode (EVM) and Program-Verify-Mode (PVM) allow to verify the effect of an erase or programming operation. In these modes an internally generated margin voltage is applied to a Flash cell, which makes reading more critical than for standard read accesses. This ensures safe standard accesses after correct verification. To get the contents of a Flash word in this mode, it has to be read in a particular way: MOV ... MOV Rwm, [Rwn] ;First (invalid) read of dedicated cell ;4 s delay to stabilize... ;...the internal margin voltage ;Second (valid) read of dedicated cell Rwm, [Rwn] Such a Flash verify read operation is different from the reading in the standard or in the non-verify mode. Correct verify reading needs a read operation performed twice on the same cell with an absolute time delay of 4 s which is needed to stabilize the internal margin voltage applied to the cell. To verify that a Flash cell was erased or programmed properly, the value of the second verify read operation has to be compared against FFFFH or the target value, respectively. Clearing bit FWE to `0' exits the Flash verify modes and returns to the Flash non-verify mode. In Flash non-verify mode all Flash locations can be read as usual (via indirect addressing modes), which is not possible in Flash programming or Flash erase mode (see EVM and PVM). 19 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Flash Protection If active, Flash protection prevents data operand accesses and program branches into the on-chip Flash area from any location outside the Flash memory itself. Data operand accesses and branches to Flash locations are exclusively allowed for instructions executed from the Flash memory itself. Erasing and programming of the Flash memory is not possible while Flash protection is active. Note: A program running within the Flash memory may of course access any location outside the Flash memory and even branch to a location outside. However, there is no way back, if Flash protection is active. Flash protection is controlled by two different bits: * The user-accessible write-only Protection Activation bit (RPROT) in register FCR and * The one-time-programmable Protection Enable bit (UPROG). Bit UPROG is a `hidden' one-time-programmable bit only accessible in a special mode, which can be entered eg. via a Flash EPROM programming board. Once programmed to `1', this bit is unerasable, ie. it is not affected by the Flash Erase mechanism. To activate Flash Protection bit UPROG must have been programmed to `1', and bit RPROT in register FCR must be set to `1'. Both bits must be `1' to activate Flash protection. To deactivate Flash Protection bit RPROT in register FCR must be cleared to `0'. If any of the two bits (UPROG or RPROT) is `0', Flash protection is deactivated. Generally Flash protection will remain active all the time. If it has to be deactivated intermittently, eg. to call an external routine or to reprogram the Flash memory, bit RPROT must be cleared to `0'. To access bit RPROT in register FCR, an instruction with a `mem, reg' addressing mode must be used, where the first operand has to represent the FCR address (any even address within the active address space of the Flash memory) and the second operand must refer to a value which sets the RPROT bit to `0', eg.: MOV FCR, ZEROS ;Deactivate Flash Protection RPROT is the only bit in the FCR which can be accessed in Flash standard mode without having to enter the Flash writing mode. Other bits in the FCR are not affected by such a write operation. However, this access requires an instruction executed out of the internal Flash memory itself. After reset bit RPROT is set to '1'. For devices with protection disabled (UPROG='0') this has no effect. For devices with protection enabled this ensures that program execution starts with Flash protection active from the beginning. Note: In order to maintain uninterrupted Flash protection, be sure not to clear bit RPROT unintentionally by FCR write operations. Otherwise the Flash protection is deactivated. Semiconductor Group 20 06May97@14:10h Intermediate Version C167CR-16F Flash Programming Algorithm The figure below shows the recommended Flash programming algorithm. The following example describes this algorithm in detail. Figure 5 Flash Programming Algorithm 21 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Flash Programming Example This example describes the Flash programming algorithm. A source block of code and/or data within the first 32 KBytes of segment 0 is copied (programmed) to a target block within the Flash memory, which is mapped to segment 1 in this case. The start and the end address of the source block to be copied are specified by the parameters SRC_START and SRC_END respectively. The target Flash memory block begins at location FLASH_START. This example uses 32-bit Flash programming. Segments 255...3 01'0000H DPP3 00'C000H 03'0000H FLASH_START SRC_END SRC_START 00'0000H Source Block in External Memory is programmed to Target Block DPP1 DPP0 Source Block DPP2 01'0000H Target Block in on-chip Flash Figure 6 Memory Allocation for Flash Programming Example Note: This example represents one possibility how to program the Flash memory. Other solutions may differ in the way they provide the source data (eg. without external memory), but use the same Flash programming algorithm. The FCR has been defined with an EQU assembler directive. Accesses to bits of the FCR are made via an auxiliary GPR, as the FCR itself is not bit-addressable. The shown example uses the following assumptions: * Pin VPP receives a proper VPP supply voltage. * The C167CR-16F runs at 20 MHz CPU clock (absolute time delays refer to this). * The Flash memory is mapped to segment 1. All DPPs are set correctly. Semiconductor Group 22 06May97@14:10h Intermediate Version C167CR-16F * Enter writing mode via unlock sequence (prerequisite for any programming or erase operation). MOV MOV CALL FCR, Rwn [Rwn], Rwn cc_UC, WAIT_10 ;Dummy write to the FCR ;Both operands use the same GPR ;Delay for 10 s * Program the FCR register with a value that selects the desired operating mode. Note that this does not yet start the programming operation itself. MOV R15, #1000 0000 1010 ; #xxxx xxxx xxxx ; #xxxx xxxx xxxx ; #xxxx xxxx x01x ; #xxxx xxxx 1xxx ; #1xxx xxxx xxxx DPP1:pof FCR, R15 0001B xxx1:FWE='1': Enable Flash write operations xx0x:FEE='0': Select programming mode xxxx:CKCTL='01':102.4 s prog.pulse(@20MHz) xxxx:WDWW='1':Select 32-bit progr. mode xxxx:FWMSET='1':Stay in writing mode ;Write Value to FCR using 16-bit access MOV * Initialize pointers and counter for the first transfer of the programming algorithm. The source data block is accessed via the pointer SRC_PTR, initialized with SRC_START. All read operations via SRC_PTR use DPP2, which selects data page 1 in this example. The Flash memory must be accessed indirectly and uses the pointer FLASH_PTR, initialized with FLASH_START. The counter DWCOUNT defines the number of doublewords to be programmed. * Test for correct VPP margin at pin VPP before a programming operation is started. If bit VPPREV reads `1', the programming voltage is correct and the algorithm can be continued. Otherwise, the programming routine could wait in Flash writing mode until VPP reaches its correct value and resume programming then, or it could exit writing mode. MOV R15, DPP1:pof FCR JB R15.4, Vpp_OK1 ... Vpp_OK1: ;Read FCR contents using 16-bit access ;Test VPP via bit VPPREV (= FCR.4) ;VPPREV='0': Exit programming procedure ;VPPREV='1': Test Okay! Continue 23 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version * Load source values and initialize loop counter (PCOUNT) with the maximum number of programming trials (PNmax) to be performed before exiting the routine with a failure. Each trial means applying a pulse of 102.4 s to the selected words in the Flash memory. According to the maximum cumulated programming time of 2.5 ms allowed per cell, PNmax must be `25' here. The doubleword at memory location [SRC_PTR] is loaded into two auxiliary registers DATAWR1 and DATAWR2. * Program one doubleword stored in the auxiliary data registers to the Flash memory location [FLASH_PTR]. FLASH_PTR is not incremented here, since in 32-bit programming mode the hardware automatically arranges the two data words correctly. The execution of the second write instruction automatically starts the programming of the entire double word. This instruction sequence must not be interrupted. MOV MOV [FLASH_PTR], DATAWR1 [FLASH_PTR], DATAWR2 ;Write low word to Flash ;Write high word to Flash, starts prog. * Wait until programming time elapsed (102.4 s in this example), which depends on bit field CKCTL in the FCR register and on the CPU clock frequency. End of programming is detected by polling the FBUSY flag in the FCR register. The Flash memory switches to PVM mode automatically. WAIT_PROG: MOV R15, DPP1: pof FCR JB R15.2, WAIT_PROG ... ;Polling Loop to check bit FBUSY ;Read FCR contents using 16-bit access ;Loop while bit FBUSY (FCR.2) is `1' ;Continue in PVM mode, when FBUSY is `0' * Verify VPP validity during programming to make sure VPP did not exceed its valid margins during the programming operation. Otherwise programming may have not been performed properly. The FCVPP flag is set to `1' in case of this error condition. If FCVPP reads `1', the programming routine can abort, when VPP still fails, or repeat the programming operation, when VPP proves to be stable now. Semiconductor Group 24 06May97@14:10h Intermediate Version C167CR-16F * Perform Program-Verify operation and compare with source data in order to check whether a programming operation was performed correctly. PVM reading consists of two identical Flash read instructions with 4 s delay in between. This example uses CMP instructions to access the Flash memory. In case of a mismatch the programming routine repeats the programming cycle provided that the maximum number of attempts was not yet reached. PVM reading and data comparison must be performed on both words of the double word to be tested. CMP CALL CMP JMP MOV ADD CMP CALL CMP JMP ... DATAWR1, [FLASH_PTR] cc_UC, WAIT_4 DATAWR1, [FLASH_PTR] cc_NZ, PROG_FAILED R15, FLASH_PTR R15, #0002H DATAWR2, [R15] cc_UC, WAIT_4 DATAWR2, [R15] cc_NZ, PROG_FAILED ;1st step of PVM read (low word) ;Delay for 4 s ;2nd step of PVM read (low word) ;Reprogram on mismatch if (PCOUNT)>0 ;Aux. pointer to upper word of doubleword ;1st step of PVM read (high word) ;Delay for 4 s ;2nd step of PVM read (high word) ;Reprogram on mismatch if (PCOUNT)>0 ;Programming OK. Go on with next step. * Check number of programming attempts to decide, if another programming attempt is allowed. PCOUNT is decremented by `1' upon each unsuccessful programming attempt. If it expires, the failing Flash cells are classified as unprogrammable and should be left out. This failure is very unlikely to occur. However, it should be checked for safe programming. Note: This step is taken only in case of a program verify mismatch. * Check for last doubleword and increment pointers to decide, if another programming cycle is required. The auxiliary counter DWCOUNT is decremented by `1' after each successful double word programming. If it expires, the complete data block is programmed and the programming routine is exited successfully. Otherwise source and target pointers (SRC_PTR and FLASH_PTR) are incremented to the next doubleword to be programmed. * Disable Flash programming operations and exit routine, when the Flash memory block was programmed successfully or when a failure occurred. In either case bit FWE of the FCR is reset to `0' and the programming routine is exited. This means that the Flash non-verify mode is entered again, where the FCR stays accessible but Flash memory locations can be read normally again using indirect addressing. For returning to the Flash standard mode, bit FWMSET of the FCR must be reset to `0' by the calling routine. The programming routine may return an exit code that indicates correct programming or identifies the type of error. 25 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Flash Erase Algorithm The figure below shows the recommended Flash erase algorithm. The following example describes this algorithm in detail. Figure 7 Flash Erase Algorithm Semiconductor Group 26 06May97@14:10h Intermediate Version C167CR-16F Flash Erase Example This example describes the Flash erase algorithm. The four banks of the Flash memory can be erased separately. The algorithm erases the Flash memory bank, which is selected by bitfield BE in the FCR. Start address and size of the selected Flash bank have to be considered. Note: Before a bank can be erased, all its contents must be programmed to `0000H'. This is required by the physics of the Flash memory cells and is done with the Flash programming algorithm already described. Segments 255...3 03'0000H 02'E000H 02'8000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Note: In this example the lower 32 KBytes of the Flash memory are mapped to segment 1. They could be mapped to segment 0 as well, however. Bank 3 Bank 2 8 KByte 24 KByte Bank 1 01'C000H AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 48 KByte Bank 0 48 KByte 01'0000H 00'0000H Segment 0 Figure 8 Memory Banking for Flash Erasure The FCR has been defined with an EQU assembler directive. Accesses to bits of the FCR are made via an auxiliary GPR, as the FCR itself is not bit-addressable. The shown example uses the following assumptions: * Pin VPP receives a proper VPP supply voltage. * The C167CR-16F runs at 20 MHz CPU clock (absolute time delays refer to this). * The Flash memory is mapped to segment 1. All DPPs are set correctly. 27 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version * Enter writing mode via unlock sequence (prerequisite for any programming or erase operation). MOV MOV CALL FCR, Rwn [Rwn], Rwn cc_UC, WAIT_10 ;Dummy write to the FCR ;Both operands use the same GPR ;Delay for 10 s * Program the FCR register with a value that selects erase mode. Note that this does not yet start the erase operation itself. MOV R15, #1000 00XX 0100 ; #xxxx xxxx xxxx ; #xxxx xxxx xxxx ; #xxxx xxxx x10x ; #xxxx xxXX xxxx ; #1xxx xxxx xxxx DPP1:pof FCR, R15 0011B xxx1:FWE='1': Enable Flash write operations xx1x:FEE='1': Select erase mode xxxx:CKCTL='10':1.64 ms erase pulse(@20MHz) xxxx:BE='xx': Select the desired bank(3..0) xxxx:FWMSET='1':Stay in writing mode ;Write Value to FCR using 16-bit access MOV * Initialize target pointer with the start address of the selected Flash memory bank. The Flash memory must be accessed indirectly and uses the pointer FLASH_PTR. This pointer will apply to DPP0 or DPP1, which are expected to select data pages 4 or 5, respectively. * Test for correct VPP margin at pin VPP before an erase operation is started. If bit VPPREV reads `1', the erase voltage is correct and the algorithm can be continued. Otherwise, the erase routine could wait in Flash writing mode until VPP reaches its correct value and resume erasing then, or it could exit writing mode. MOV R15, DPP1:pof FCR JB R15.4, Vpp_OK2 ... Vpp_OK2: ;Read FCR contents using 16-bit access ;Test VPP via bit VPPREV (= FCR.4) ;VPPREV='0': Exit erase procedure ;VPPREV='1': Test Okay! Continue * Initialize loop counter (PCOUNT) with the maximum number of erase trials (ENmax) to be performed before exiting the routine with a failure. Each trial means applying a pulse of 10 ms to the selected Flash memory bank. According to the maximum cumulated erase time of 30 s allowed per cell, ENmax must be `3000' here. * Erase selected Flash memory bank by writing to a Flash memory location using the target address as write data. MOV [FLASH_PTR], FLASH_PTR ;Write address to Flash, starts erasing * Wait until erase time elapsed, which depends on bit field CKCTL in the FCR register and on the CPU clock frequency (10 ms in this example). End of erasing is detected by polling the FBUSY flag in the FCR register. The Flash memory switches to EVM mode automatically. WAIT_ERASE: MOV R15, DPP1: pof FCR JB R15.2, WAIT_ERASE ... ;Polling Loop to check bit FBUSY ;Read FCR contents using 16-bit access ;Loop while bit FBUSY (FCR.2) is `1' ;Continue in EVM mode, when FBUSY is `0' Semiconductor Group 28 06May97@14:10h Intermediate Version C167CR-16F * Verify VPP validity during erasing to make sure VPP did not exceed its valid margins during the erase operation. Otherwise erasing may have not been performed properly. The FCVPP flag is set to `1' in case of this error condition. If FCVPP reads `1', the erase routine can abort, when VPP still fails, or repeat the erase operation, when VPP proves to be stable now. * Perform Erase-Verify operation and compare with `FFFFH' in order to check whether an erase operation was performed correctly. EVM reading consists of two identical Flash read instructions with 4 s delay in between. This example uses CMP instructions to access the Flash memory. In case of a mismatch the erase routine repeats the erase cycle provided that the maximum number of attempts was not yet reached. MOV CMP CALL CMP JMP ... R15, ONES R15, [FLASH_PTR] cc_UC, WAIT_4 R15, [FLASH_PTR] cc_NZ, ERASE_FAILED ;Load auxil. ;1st step of ;Delay for 4 ;2nd step of ;Re-erase on ;Erasing was GPR with anticipated value EVM read s EVM read mismatch if (PCOUNT)>0 OK. Go on with next step. * Check number of erase attempts to decide, if another erase attempt is allowed. PCOUNT is decremented by `1' upon each unsuccessful erase attempt. If it expires, the failing Flash memory bank is classified as unerasable. This failure is very unlikely to occur. However, it should be checked for safe erasing. Note: This step is taken only in case of a erase verify mismatch. * Check for last word and increment pointers to decide, if another cell must be verified. The target pointer (FLASH_PTR) is incremented to the next word to be verified and checked against the upper limit of the respective bank. If the target pointer exceeds the bank limit, the erase routine is exited successfully. * Disable erase operations and exit routine, when the Flash memory bank was erased successfully or when a failure occurred. In either case bit FWE of the FCR is reset to `0' and the erase routine is exited. This means that the Flash non-verify mode is entered again, where the FCR stays accessible but Flash memory locations can be read normally again using indirect addressing. For returning to the Flash standard mode, bit FWMSET of the FCR must be reset to `0' by the calling routine. The erase routine may return an exit code that indicates correct erasing or identifies the type of error. 29 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Fundamentals of Flash Technology The Flash memory included in the C167CR-16F combines the EPROM programming mechanism with electrical erasability (like an EEPROM) to create a highly reliable and cost effective memory. A Flash memory cell consists of a single transistor with a floating gate for charge storage like an EPROM, uses a thinner gate oxide, however. The programming mechanism of a Flash cell is based on `hot' electron injection which works as follows: The cell control gate and drain are set to a high voltage and the cell source is grounded. This high voltage between drain and source forces `hot' electrons supplied from the source to enter the channel. Attracted by the high voltage on the cell's control gate there, free electrons are trapped in the floating gate. The amount of negative charge on the floating gate is basically determined by the length and the number of programming pulses applied to the cell. A special read operation, Program-Verify, is provided for verifying that the charge put onto the floating gate represents a proper `0'. Figure 9 Flash Memory Cell Programming Mechanism The cell erase mechanism is based on `Fowler-Nordheim' tunnelling which works as follows: A high voltage is applied to the cell's source whilst the control gate grounded. The cell's drain is disconnected in this case. Attracted by the high voltage on the cell's source, electrons migrate from the floating gate to the source. The amount of negative charge removed from the floating gate is basically determined by the length and the number of erasing pulse applied to the cell. A special read operation, Erase-Verify, is provided for verifying that the charge remaining on the floating gate represents a proper `1'. Unlike a standard EEPROM, where individual bytes can be erased, the Flash memory of the C167CR-16F is erased block-wise which means that the high voltage is applied to all cells belonging to one block simultaneously. One requirement for performing proper Flash programming and erase operations is to have all cells of a block set to a minimum threshold level before the operation is started. A cell erasing faster than others could have a threshold voltage too low or negative. In this case the corresponding transistor could become conductive and affect other cells placed in the same column of the transistor array. Thus, all cells of that column could erroneously be read as `1' instead of `0'. Semiconductor Group 30 06May97@14:10h Intermediate Version C167CR-16F To avoid this possible malfunction, the user must equalize the amount of charge on each cell by programming all cells of one block to `0' before performing a block erasure. Figure 10 Flash Memory Cell Erase Mechanism The introduced erase algorithm meets this requirement. In combination with the Flash technology used, it provides a tight erase threshold voltage distribution, generating a sufficient margin even to cells erasing faster than others. Figure 11 Flash Erasure 31 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C167CR-16F-LM .....................................................................................................0 to +70 C SAF-C167CR-16F-LM ................................................................................................. -40 to +85 C Storage temperature (TST)......................................................................................... - 65 to +125 C Voltage on VCC pins with respect to ground (VSS) ....................................................... -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) ...................................................-0.5 to VCC +0.5 V Input current on any pin during overload condition .................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VIN Semiconductor Group 32 06May97@14:10h Intermediate Version C167CR-16F DC Characteristics VCC = 5 V 10 %; TA = 0 to +70 C TA = -40 to +85 C Parameter VSS = 0 V; fCPU = 20 MHz; for SAB-C167CR-16F-LM for SAF-C167CR-16F-LM Symbol min. Reset active Limit Values max. 0.2 VCC - 0.1 2.0 Unit Test Condition Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) VIL SR - 0.5 V V V V V V mV V - - - - - - - VILS SR - 0.5 VIH SR 0.2 VCC + 0.9 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC VIHS SR 0.8 VCC - 0.2 HYS 400 Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) IOL = 2.4 mA VOL1 CC - 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0.45V < VIN < VCC 0.45V < VIN < VCC 5) 8) Output high voltage VOH CC 0.9 VCC 2.4 (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) 1) VOH1 CC 0.9 VCC 2.4 - 200 500 5 250 -40 - 40 - -40 - V V nA nA mA k A A A A A A Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current 4) Read/Write active current 4) ALE inactive current ALE active current 4) Port 6 inactive current 4) Port 6 active current 4) 4) IOZ1 CC - IOZ2 CC - IOV IRWH IRWL IALEL IALEH IP6H IP6L SR - 2) 3) 2) 3) 2) 3) RRST CC 50 - -500 - 500 - -500 - VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max 33 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Parameter PORT0 configuration current 4) XTAL1 input current Pin capacitance 5) (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current Symbol min. Limit Values max. -10 - 20 10 30 + 7 * fCPU 30 + 2 * fCPU 100 200 50 Unit Test Condition IP0H IP0L IIL CIO ICC IID IPD IPPR IPPW 2) 3) - -100 A A A pF mA mA A A mA VIN = VIHmin VIN = VILmax 0 V < VIN < VCC CC - CC - - - - - - f = 1 MHz TA = 25 C RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) VCC = 5.5 V 7) VPP > VCC fCPU = 20 MHz; VPP = 12 V; 32-bit programming VPP read current VPP writing current VPP during write/read VPP 11.4 12.6 V Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100% tested, guaranteed by design. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin exceeds the specified range (ie. VOV > VCC+0.5V or VOV < VSS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. 2) 3) 4) 5) 6) 7) 8) Semiconductor Group 34 06May97@14:10h Intermediate Version C167CR-16F 200 AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA ICCmax AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA 150 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA I AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA CCtyp AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 100 AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IDmax AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IDtyp AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 50 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA AA AA I [mA] 5 10 15 20 fCPU [MHz] Figure 12 Supply/Idle Current as a Function of Operating Frequency 35 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version A/D Converter Characteristics VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C167CR-16F-LM TA = -40 to +85 C for SAF-C167CR-16F-LM 4.0 V VAREF VCC+0.1 V ; VSS-0.1 V VAGND VSS+0.2 V Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol Limit Values min. max. Unit V Test Condition 1) 2) 4) 3) 4) VAIN SR VAGND tS tC CC - CC - VAREF 2 tSC 14 tCC + tS + 4TCL 2 TUE CC - LSB k k pF 5) RAREF SR - RASRC SR - CAIN CC - tCC / 165 - 0.25 tCC in [ns] 6) 7) tS in [ns] 2) 7) 7) tS / 330 - 0.25 33 Sample time and conversion time of the C167CR-16F's A/D Converter are programmable. The table below should be used to calculate the above timings. ADCON.15|14 (ADCTC) 00 01 10 11 Conversion clock TCL * 24 Reserved, do not use TCL * 96 TCL * 48 tCC ADCON.13|12 (ADSTC) 00 01 10 11 Sample clock tSC tCC tCC * 2 tCC * 4 tCC * 8 Semiconductor Group 36 06May97@14:10h Intermediate Version C167CR-16F Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table above. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. TUE is tested at VAREF=5.0V, VAGND=0V, VCC=4.9V. It is guaranteed by design for all other voltages within the defined voltage range. Please note that this test condition for VAREF represents a stress situation which should be avoided during normal operation. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. Please note that the given formula applies for direct supply of VAREF. The internal resistance of the analog voltage source can be increased by providing a support capacitance close to the VAREF pin. Not 100% tested, guaranteed by design. 2) 3) 4) 5) 6) 7) 37 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 13 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 14 Float Waveforms Semiconductor Group 38 06May97@14:10h Intermediate Version C167CR-16F AC Characteristics Definition of Internal Timing The internal operation of the C167CR-16F is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). Phase Locked Loop Operation fXTAL fCPU Direct Clock Drive fXTAL fCPU A A A A A A A TCLA TCLA A A A A A A A A A A TCLA TCLA Figure 15 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C167CR-16F. Direct Drive When pin P0.15 (P0H.7) is low (`0') during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL * DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin. 39 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Phase Locked Loop When pin P0.15 (P0H.7) is high (`1') during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (ie. fCPU = fXTAL * 4). With every fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, ie. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation D N: (N TCL)min = N TCLNOM * (1 - DN / 100) DN = (4 - N /15) [%], where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (ie. N = 3): D3 = 4 - 3/15 = 3.8%, and (3TCL)min = 3TCLNOM * (1 - 3.8 / 100) = 3TCLNOM * 0.962 (72.15 nsec @ fCPU = 20 MHz). This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Max.jitter [%] This approximated formula is valid for 1 N 40 and 10MHz fCPU 20MHz. 4 3 2 1 2 4 8 16 32 N Figure 16 Approximated Maximum PLL Jitter Semiconductor Group 40 06May97@14:10h Intermediate Version C167CR-16F AC Characteristics External Clock Drive XTAL1 VCC = 5 V 10 %; TA = 0 to +70 C TA = -40 to +85 C Parameter Oscillator period High time Low time Rise time 3) VSS = 0 V for SAB-C167CR-16F-LM for SAF-C167CR-16F-LM Symbol Direct Drive 1:1 min. max. 1000 - - 10 2) 1) 2) PLL 1:4 min. 200 10 10 - - max. 333 - - 10 2) Unit ns ns ns ns ns tOSC SR 50 t1 t2 t3 t4 SR 23 1) 2) SR 23 SR - SR - Fall time 3) 1) 2) 3) 10 2) 10 2) For temperatures above TA = +85 C the minimum value for t1 and t2 is 25 ns. The clock input signal must reach the defined levels VIL and VIH2 . Not 100% tested, guaranteed by design. Figure 17 External Clock Drive XTAL1 41 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values tA tC tF TCL * AC Characteristics Multiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C167CR-16F-LM TA = -40 to +85 C for SAF-C167CR-16F-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) max. - - - - - 5 30 - - 15 + tA 10 + tA 15 + tA 15 + tA -10 + tA - - 40 + tC 65 + tC Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA - TCL - 10 + tA - -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - 5 TCL + 5 - - Unit t5 t6 t7 t8 t9 t10 t11 t12 t13 CC CC CC CC CC CC CC CC CC Semiconductor Group 42 06May97@14:10h Intermediate Version C167CR-16F Parameter Symbol Max. CPU Clock = 20 MHz min. max. 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF - - - - 10 - tA 55 + tC + 2tA - - - 0 25 25 + tC - - - - 0 - 25 + tC 35 + tF 35 + tF 35 + tF -5 - tA - 60 + tF 20 + tA -5 + tA - - - - - - - 0 - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 25 + tC Unit RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after WR 1) ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) t14 t15 t16 t17 t18 t19 t22 t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46 SR SR SR SR SR SR SR CC CC CC CC SR CC CC CC CC CC SR ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2TCL - 25 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF -5 - tA - 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - - 43 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Parameter Symbol Max. CPU Clock = 20 MHz min. max. 50 + tC - - - - 30 + tF - - - 40 + tC 65 + tC 35 + tC 0 - 30 + tF 30 + tF - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 3TCL - 25 + tC - - - - 2TCL - 20 + tF - - Unit RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS t47 t48 t49 t50 t51 t52 t54 t56 SR CC CC CC SR SR CC CC ns ns ns ns ns ns ns ns 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF 1) It is guaranteed by design that read data are latched before the address changes. Semiconductor Group 44 06May97@14:10h Intermediate Version C167CR-16F ALE A A A A A A A A A A t5 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A23-A16 (A15-A8) BHE t6 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 38 A A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA 17 AA AA AA AA AA AA AA AA AA AA AA AA 7 AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA A AA AA AA AA 8 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AA AA AA AA AA 42 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 8 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AA AA AA AA AA 42 AA AA AA AA AA AA AA AA AA AA AA AA t16 t t39 t Address A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 14 AA AA AA AA AA AA AA AA 12 A AA A AA AA AA AA A A 46 A A A A A A A 48 A A A A A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA 22 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 12 AAA AAA AAA AAA 50 AAA t t t10 t t t t t t44 AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t10 t t t44 t t t48 A A 25 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 27 A A A A A A A A A A A A 54 A A A A A 19 A A A A 18 A A A A A Data In A A A A A A A A A A A A AA A AA AA AA A AA A AA A AA A AA A AA A AA A AA A 51 A A A A 52 A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A A A A A A A A A A 23 A A A A Data Out A A A A A A A 56 A A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA t AA AA AA AA AA AA AA AA AA AA t40 AA AA AA AA AA AA AA AA AA AA AA t t t t t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t A A A A A A A A A A A A A A A A Figure 18-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 45 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version ALE A A A A A A A A A A t5 t38 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A23-A16 (A15-A8) BHE t6 A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA A A A A A A A A A A A A A A A A A A A A Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t16 t39 t17 Address A A A A A A A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 14 AAA AAA AAA AAA AAA AAA AAA AAA 12 AA AAA A AAA AAA AAA AAA A A 46 A A A A A A A 48 A A A A A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA 22 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 12 AAA AAA AAA AAA 50 AAA t7 t8 t42 AA 10 AA AA AA AA AA AA AA AA AA AA AA AA AA AA 44 AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A t8 t42 WrCSx AA 10 AA AA AA AA AA AA AA AA AA AA AA AA AA AA 44 AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t48 AA A AA 25 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 40 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 27 AA AA AA AA AA AA AA AA AA AA AA AA 54 AA AA AA AA AA 19 AA AA AA A AA A 18 AA A AA A AA A AA A AA A Data In AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 51 AA A AA AA AA 52 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 23 AA AA AA AA Out Data AA AA AA AA AA AA AA 56 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t t t t A A A A A A A A A A A A A A A A Figure 18-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 46 06May97@14:10h Intermediate Version C167CR-16F ALE A A A A A A A A A A t5 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A23-A16 (A15-A8) BHE t6 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA38 A A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA 17 AA AA AA AA AA AA AA AA AA AA AA AA 7 AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA 9 AA A AA A AA A AA A AA A AA A AA A A AA AA A AA A AA A AA A AA A AA A AA AA 43 A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA 9 AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA 43 A A AA A AA A AA A AA A A A A A A A A A A A t16 t t39 t Address A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 15 AA AA AA AA AA AA AA AA 13 A AA A AA AA AA AA A A 47 A A A A A A A 49 A A A A A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA 22 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 13 AAA AAA AAA AAA 50 AAA t t t11 t t t t t t45 AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t11 t t t t45 t t49 A A 25 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 27 A A A A A A A A A A A A 54 A A A A A 19 A A A A 18 A A A A A Data In A A A A A A A A A A A A AA A AA AA AA A AA A AA A AA A AA A AA A AA A AA A 51 A A A A 52 A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A A A A A A A A A A 23 A A A A Data Out A A A A A A A 56 A A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA t AA AA AA AA AA AA AA AA AA AA t40 AA AA AA AA AA AA AA AA AA AA AA t t t t t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t A A A A A A A A A A A A A A A A Figure 18-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 47 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version ALE A A A A A A A A A A t5 t38 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A23-A16 (A15-A8) BHE t6 A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA A A A A A A A A A A A A A A A A A A A A Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA AA 9 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 43 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Address AA AA AA AA AA AA AA AA AA AA AA 9 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 43 AA t16 t39 t17 Address A A A A A A A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 15 AAA AAA AAA AAA AAA AAA AAA AAA 13 AA AAA A AAA AAA AAA AAA A A 47 A A A A A A A 49 A A A A A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA 22 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 13 AAA AAA AAA AAA 50 AAA t7 t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t11 t t t t t45 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A t t WrCSx AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t11 t t t45 t t49 AA A AA 25 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 40 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 27 AA AA AA AA AA AA AA AA AA AA AA AA 54 AA AA AA AA AA 19 AA AA AA A AA A 18 AA A AA A AA A AA A AA A Data In AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 51 AA A AA AA AA 52 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 23 AA AA AA AA Out Data AA AA AA AA AA AA AA 56 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t t t t A A A A A A A A A A A A A A A A Figure 18-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 48 06May97@14:10h Intermediate Version C167CR-16F AC Characteristics Demultiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C167CR-16F-LM TA = -40 to +85 C for SAF-C167CR-16F-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR Data hold after WR ALE rising edge after RD, WR max. - - - - - - 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF 15 + tF - - - 15 + tA 10 + tA 15 + tA -10 + tA 40 + tC 65 + tC - - - - 0 - - 25 + tC 15 + tF -10 + tF Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 25 + tC -10 + tF - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + 2tA + tF 1) TCL - 10 + 2tA + tF 1) - Unit t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26 CC CC CC CC CC CC SR SR SR SR SR SR SR CC CC CC TCL - 10 + tF - - 49 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Parameter Symbol Max. CPU Clock = 20 MHz min. max. - 10 - tA 55 + tC + 2tA - - - 25 + tC 50 + tC - - - - 30 + tF 5 + tF - - 0 + tF -5 - tA - 10 + tF 20 + tA -5 + tA - - 40 + tC 65 + tC 35 + tC 0 - - -10 + tF 10 + tF Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 0 + tF -5 - tA - TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - -10 + tF TCL - 15 + tF max. - 10 - tA 3TCL - 20 + tC + 2tA - - - 2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - Unit Address hold after WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR 2) t28 t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57 CC CC SR CC CC CC SR SR CC CC CC SR SR SR CC CC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1) 2) RW-delay and tA refer to the next following bus cycle. It is guaranteed by design that read data are latched before the address changes. Semiconductor Group 50 06May97@14:10h Intermediate Version C167CR-16F ALE A A A A A A A A A A t5 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A23-A16 A15-A0 BHE t6 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 38 A A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA 17 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AA AA 8 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AA AA AA AA AA 42 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 8 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA AA AA AA AA AA AA 42 AA AA AA AA AA AA AA AA AA AA AA AA t16 t t39 t Address t t14 t12 t46 t48 t AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA 22 AA AA AA AA AA AA AA AA AA AA AA AA 12 AA AA AA AA 50 AA t t t t48 A A A A 26 A A A A A A A A A A A A A A A A A A A A A A A A 41 A A A A A A A A A A A A A A A A A 28 A A A A A A A A A A A A A A A A A A A A A A A A 55 A A A A A A 20 A A A A A A A 18 A A A A A A A A A A Data In A A A A A A A A A A A A A A A A A A A A A A A A AA A AA A AA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A 51 A A A A A 53 A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A A A A A A A A AA A AA A AA 24 A AA A AA A AA A Out AA Data A AA A AA A AA A AA A AA A AA A AA 57 A AA A AA AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA t t A A A A A A A A A A A t t t t t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t Figure 19-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE 51 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version ALE A A A A A A A A A A t5 t38 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A23-A16 A15-A0 BHE t6 A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA A A A A A A A A A A A A A A A A A A A A Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t16 t39 t17 Address t8 t42 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t8 t42 WrCSx AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A AA A 26 AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA AA 41 AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA A 28 AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A 55 AA A AA AA AA AA 20 AA AA AA A AA A 18 AA A AA A AA A AA A AA A Data In AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA A 14 AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 12 AA AA A 51 AA A AA AA AA 53 AA AA AA AA AA 46 AA AA AA AA AA AA AA AA AA AA AA AA AA AA 48 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 24 AA AA A AA AA A AA AA A AA AA Data Out AA A AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA 57 A AA AA A AA AA A AA AA A AA AA 22 A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 12 AA AA A A AA AA A AA AA A AA AA 50 A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 48 AA t t t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A t t A A A A A A A A A A A t t t t t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t Figure 19-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 52 06May97@14:10h Intermediate Version C167CR-16F ALE A A A A A A A A A A t5 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A23-A16 A15-A0 BHE t6 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA38 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 9 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 43 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 9 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 43 AA AA AA AA t16 t A A A A A A A A A A A t39 t17 Address t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A t15 t13 t47 t49 AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t WrCSx A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA 22 AA AA AA AA AA AA AA AA AA AA AA AA 13 AA AA AA AA 50 AA t t t t49 A A A A 26 A A A A A A A A A A A A A A A A A A A A A A A A 41 A A A A A A A A A A A A A A A A A A A 28 A A A A A A A A A A A A A A A A A A A A A A A A 55 A A A A A A 21 A A A A A A A 18 A A A A A A A A A A Data In A A A A A A A A A A A A A A A A A A A A A A A A AA A AA A AA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A 51 A A A A A 68 A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A A A A A A A A AA A AA A AA 24 A AA A AA A AA A Out AA DataA AA A AA A AA A AA A AA A AA A AA 57 A AA A AA AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA t t A A A A A A A A A A A t t t t t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t Figure 19-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE 53 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version ALE A A A A A A A A A A t5 t38 CSx AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A23-A16 A15-A0 BHE t6 A A A A A A A A A A A A A AA AA AA AA AA AA AA AA AA AA AA AA AA A A A A A A A A A A A A A A A A A A A A Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t16 t39 t17 Address t9 t43 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t9 t43 WrCSx AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A AA A 26 AA A AA A AA A AA A AA A AA A AA A AA A AA AA AA AA AA AA AA AA 41 AA AA AA AA AA AA AA AA AA AA AA AA AA AA A AA A 28 AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A 55 AA A AA AA AA AA 21 AA AA AA A AA A 18 AA A AA A AA A AA A AA A Data In AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA AA A 15 AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 13 AA AA A 51 AA A AA AA AA 68 AA AA AA AA AA 47 AA AA AA AA AA AA AA AA AA AA AA AA AA AA 49 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 24 AA AA A AA AA A AA AA A AA AA Data Out AA A AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA 57 A AA AA A AA AA A AA AA A AA AA 22 A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A AA AA A 13 AA AA A A AA AA A AA AA A AA AA 50 A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 49 AA t t t t A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A t t A A A A A A A A A A A t t t t t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t Figure 19-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 54 06May97@14:10h Intermediate Version C167CR-16F AC Characteristics CLKOUT and READY VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C167CR-16F-LM TA = -40 to +85 C for SAF-C167CR-16F-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 50 - - 5 5 10 + tA - - - - - 0 + 2tA + tC + tF 2) Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 5 TCL - 10 - - 0 + tA 15 0 2TCL + 15 15 0 0 max. 2TCL - - 5 5 10 + tA - - - - - Unit t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CC CC CC CC CC SR SR SR SR SR SR 50 20 15 - - 0 + tA 15 0 65 15 0 0 ns ns ns ns ns ns ns ns ns ns ns TCL - 25 ns + 2tA + tC + tF 2) Notes 1) 2) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. 55 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version CLKOUT ALE Command RD, WR Sync READY Async READY AA AA AA AA MUX/Tristate Running cycle AA AA AA AA A AA A AA AA A AA A AA AA A AA AA A AA A AA AA A AA A AA A A AA AA A AA AA A AA 32 AA A AA A 33 A AA AA A A AA AA A AA A AA AA A A AA AA A AA AA A AA A AA A A AA AA A AA AA A AA A AA A A AA AA AA A 30 AA A A AA AA A AA AA A A AA AA A AA AA A AA A AA A A AA AA A AA 29 AA A A AA AA A AA AA A AA A A AA AA A AA AA A A AA AA A AA 31 AA A 34 A AA AA A AA AA AA A A AA AA A AA AA A A AA AA A AA A AA A A AA AA A AA A AA A AA A A A AA AA AA A A AA AA A AA A AA A A AA AA A AA A AA A A AA AA A AA A AA A A AA AA A AA A AA A A AA AA A AA AA A AA A A AA AA A AA AA A AA AA A AA AA A A AA AA A AA AA A A AA AA A AA AA A AA A A AA AA AA A AA A A AA AA AA A A AA AA A AA AA A A AA AA A AA AA A AA A A AA AA AA A A AA AA A AAA AA A A AA AA A AAA AA A A AA AA A AAA 2) AA A A AA AA A AAA AA A A AA AA A AAA AA A A AA AA A AAA AA A AA A A AA AAA AA A A AA AA A AAA AA A A AA AA A AAA AA A A AA AA A AAA AA A A AA AA A AAA AA A AAA 35 A AA 36 AA 35 AA A 36 A AA A A A AA A AA A AA AAA A AA A AA A AA AA A A AA AAA AA A A A AA AA A AA A AA AAA AA A A A AA AA A AA A AA AAA AA A A A AA AA A AA AAA AA A A A AA AA A AA AAA AA A A AA A AA AAA 3) 3) A AA AA A A A AA AA A AA AAA AA A A A AA AA A AA AAA AA A A A AA AA A AA A AAA AA A A AA AAA AA A A AA AAA AA A A AA AAA 4) AA A A AA AAA AA A 59 A AA 59 AAA 60 A 58 AA A AA A 58 A AA AA AAA AA A AA A AA A A AA AA AAA AA A AA A AA AA AA A A AA AAA A AA AA AA A A AA AA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA 3) A AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 3) A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAA AA AA A AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA AA A AA AA A AA AA 37 A 5) AA AA AA AA see 6) 1) READY waitstate AA 6) AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA t t t t t t 7) t t t t t t t t t t Figure 20 CLKOUT and READY Notes 1) 2) 3) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here. 4) 5) 6) 7) Semiconductor Group 56 06May97@14:10h Intermediate Version C167CR-16F AC Characteristics External Bus Arbitration VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for SAB-C167CR-16F-LM TA = -40 to +85 C for SAF-C167CR-16F-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other bus signals release Other bus signals drive max. - 20 20 20 25 20 25 20 - - - -5 - -5 20 - - - -5 - -5 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. - 20 20 20 25 20 25 ns ns ns ns ns ns ns Unit t61 t62 t63 t64 t65 t66 t67 SR CC CC CC CC CC CC 57 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version CLKOUT A A A A A A A A A A A A A A A A A A A A A A A A A A A A t61 A A A A A A A A A A A A A A A HOLD HLDA 1) BREQ CSx (On P6.x) Other Bus Signals AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A A AA A A A AA AA A 63 A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A AA A AA A AA 62 A A AA A AA A A AA A A AA A A AA A A AA A A AA A 2) A AA A A AA A A AA A A AA A AA A AA A AA A AA 64 A AA A 3) A A AA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A A A A A A 66 AA A A AA A AA AA AA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA t t t t 1) Figure 21 External Bus Arbitration, Releasing the Bus Notes 1) 2) 3) The C167CR-16F will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. The CS outputs will be resistive high (pullup) after t64. Semiconductor Group 58 06May97@14:10h Intermediate Version C167CR-16F AA 2) AA AA AA AA AA AA AA AA AA AA AA AA AA AA 61 AA AA AA AA AA AA AA AA AA AA AA HOLD AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA HLDA AA AA AA AA AA AA AA AA AA 63 AA A AA A AA A AA A AA A AA A AA A BREQ AA A AA A AA A AA AA AA AA AA 65 AA A AA A AA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A CSx AA A AA A AA A AA A (On P6.x) AA AA AA AA AA AA 67 AA A AA A AA A AA A A Other Bus AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A Signals A CLKOUT A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 62 AA A A AA A AA AA AA AA AA AA AA AA t t AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 62 A AA AA A AA A AA A A A 1) A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 62 AA A A AA A AA A AA A AA A AA A AA A AA A AA AA t t t t t Figure 22 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167CR-16F requesting the bus. The next C167CR-16F driven bus cycle may start here. 2) 59 Semiconductor Group C167CR-16F 06May97@14:10h Intermediate Version Package Outline Plastic Package, P-MQFP-144-4 (SMD) (Plastic Metric Quad Flat Package) Dim A A1 A2 B C D D3 e E E3 L L1 K mm Min 0.25 0.22 0.13 Typ Max 4.07 0.010 0.38 0.009 0.23 0.005 Min inches Typ Max 0.160 VR02061A 3.17 3.42 3.67 0.125 0.135 0.144 0.015 0.009 30.95 31.20 31.45 1.219 1.228 1.238 22.75 0.65 0.896 0.026 D1 27.90 28.00 28.10 1.098 1.102 1.106 30.95 31.20 31.45 1.219 1.228 1.238 22.75 1.60 0.896 0.063 E1 27.90 28.00 28.10 1.098 1.102 1.106 0.65 0.80 0.95 0.026 0.031 0.037 0(min.), 7(max.) Figure 23 Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 60 Dimensions in mm |
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